The Z80 is my favorite CPU platform of all time. I have been a fan ever since a friend of a friend gave me a Z80 Programming Handbook back in 1990. On the drive home, I familiarized myself with every detail of the hardware architecture, as well as the programming language, just as I had done years before with the 6502. I found the Z80 to be so much more user-friendly than the 6502 and more powerful. I immediately started buying parts and experimenting with this powerful and flexible CPU.
Over the years I built many Z80-based boards and eventually replaced the 6502 in my consulting designs with the Z80. Back then (early 90s), I never really used any of the Zilog peripheral ICs, meaning I never really got to experiment with the Vectored Interrupt feature of the Z80. Some time ago I acquired an RC2014 Kit and recently got around to experimenting with it. It revived my love of the Z80, and I found myself wanting to build a Z80 retro computer. I ordered some parts to build a Z80 trainer / demo board, this time experimenting with the Zilog peripherals, at least, those that are still available.
This project is just a test of my memory, in that I literally just sat down with a breadboard and started putting stuff together from memory. I didn’t have a schematic pre-drawn. I only had ideas in my head. The only reference I used was having my tablet set up so I could access the datasheets for the various IC pinouts. The initial build is more or less just a test bed for proving out various modifications and I/O options.
This article will actually end up being a kind of build blog with several variants, whose end design will roll into a more permanent build with a custom PCB. Back in the day when I built Z80 designs, the prototypes were either wire-wrapped or point-to-point on perf boards, as in this project. It will be nice to actually use a breadboard with the Z80.
Let the Experiments Begin
The first thing I did was place a Z80 close to the middle of the breadboard, and then I tried to figure out efficient placement of the SRAM, EEPROM, and address decoder. I also had to account for the reset circuitry and the clock, which is a TTL oscillator. So let me give a parts list for what you currently see and how everything is connected.
- Z80B (6 MHz version)
- 62256 (32K SRAM)
- X28C256 (32K EEPROM)
- 4 MHz TTL Oscillator
- 74LS138 (3-to-8 line decoder)
I will be developing the schematic as I complete each subsection. In the photo above you can see my initial parts placement. All the ICs have the power connections already made to the busses on the breadboard. The clock signal from the oscillator to the Z80 is connected. A0-A2 are connected from the Z80 to the 74LS138 inputs. All the pins on the SRAM that also connect to the EEPROM are also completed. In order to complete the initial testing the following components were added:
- 74LS04 (Hex Inverter)
- 74LS32 (Quad 2-Input OR Gate)
- 74LS374 (3-State Octal Edge-Triggered D-Type Flip-Flop)
- TL7705ACP (Reset Supervisor)
- 10-Segment LED Bar Graph Display (8-bit Output Indicator)
The next step was to make the connections from memory to the Z80, however, in order to complete this, I needed to add some logic. So in this photo I moved the oscillator down and added the remaining parts. More of the 74LS04 will be used later, but for now it is simply providing an inverted output of the A15 line, which tells whether we’re accessing ROM or RAM. The reset supervisor provides a power-on reset signal to the Z80 and eventually to an 8255 PPI.
Note that the Z80 uses an active-low reset signal, while the 8255 uses an active-high reset signal. The TL7705ACP provides both signals. The push button to the left of it provides a manual reset. The 74LS138 is not visible in this photo, however it is still just to the right of the Z80 as in the previous photo. To the right of the 74LS138 is a 74LS32, which is a Quad 2-Input OR gate, which is used to combine some of the Z80 signals. The output of the 74LS32 is only low when both inputs are low, so this is good for generating an active-low enable output from two active-low inputs.
The four gates are wired as follows:
- Gate 1 inputs come from /MEMREQ and /RD, and the output becomes /MEMREAD, which goes to the /OE on the EEPROM and SRAM.
- Gate 2 inputs come from /MEMREQ and /WR, and the output becomes /MEMWRITE, which goes to the /WR pin on the SRAM.
- Gate 3 inputs come from /IOREQ and /RD, and the output becomes /IOREAD, which goes to the appropriate pins on the various I/O devices.
- Gate 4 inputs come from /IOREQ and /WR, and the output becomes /IOWRITE, which goes to the appropriate pins on the various I/O devices.
For memory, the /CS signal comes from A15, which goes directly to the EEPROM and through an inverter to SRAM. In this manner, when A15 is low ($0000-$7FFF), the EEPROM is selected. When A15 is high ($8000-$FFFF), the SRAM is selected. For I/O, /IOREAD and /IOWRITE work with the outputs from the 74LS138 to enable the various I/O devices.
For the initial build, I’m only driving a 74LS374, which acts as a latched 8-bit output. In this case, it drives 8 LEDs from the 10-segment bar graph display. Every time there is a write to port $00, the contents of the A register are latched into the 74LS374.
This video shows the Z80 counting from $35 to $01 and displaying that counter output on the LED bar graph.[LCD PHOTO]
The next interface I’m going to test is connecting a Hitachi-compatible parallel character LCD. This will require a 74LS02 Quad NOR gate. This is used similar to the 74LS32, except that the output is inverted. The output of the 74LS02 is only high when both inputs are low, so this is good for generating an active-high enable output from two active-low inputs.
Since the LCD has an active-high enable pin, this gives the correct output. Even while combining the /IOREQ and /RD or the /IOREQ and /WR lines, there is still the possibility of a timing issue with the LCD.
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